1. Field of the Invention
The present invention relates to a semiconductor device used in a high frequency device, and particularly relates to a semiconductor device having a reduced chip size and improved high frequency characteristics.
2. Description of the Related Art
FIG. 4 illustrates an example of a junction field effect transistor (hereinafter, referred to as J-FET) used in high frequency devices.
FIG. 4 is a plan view showing a J-FET 200. The J-FET 200 has active regions 35 provided on a semiconductor substrate 20 forming a semiconductor chip. The active regions 35 are isolated by an isolation region 23. In this example, the two active regions 35 are provided, and both have the same configuration.
The active regions 35 each have the following configuration. Specifically, source regions, drain regions, and gate regions 27 are provided in a channel region 24, in a stripe pattern. Source electrodes 29 and drain electrodes 30 are respectively provided on and connected to the source regions and the drain regions. A source pad electrode 29p and a drain pad electrode 30p are respectively provided outside the active regions 35, and are respectively connected to the source regions and the drain regions. This technology is described for instance in Japanese Patent Application Publication No. Hei 8-227900 (p. 2 and FIG. 6).
FIGS. 5A and 5B are respectively a cross-sectional view of the cross section taken along the line c-c in FIG. 4 and an enlarged plan view of the active region 35. FIG. 5A illustrates a single set of the source region 25, the gate region 27, and the drain region 26, and an electrode layer formed on surfaces of these regions is omitted in FIG. 5B.
As shown in FIG. 5A, the semiconductor substrate 20 is obtained, for example, by stacking a p type semiconductor layer 22 on a p type silicon semiconductor substrate 21. A channel region 24 is provided on a surface of the semiconductor substrate 20, the channel region 24 being obtained by isolating an n type semiconductor region with the isolation region 23, which is a heavily-doped p type impurity region. In the n type channel region 24, the n+ type source region 25 and the n+ type drain region 26 are provided in a stripe pattern. Between the source region 25 and the drain region 26, the gate region 27 is formed in a stripe pattern. Here, conductivity types such as p+, p and p− belong in one general conductivity type, and conductivity types such as n+, n and n− belong in another general conductivity type.
The J-FET 200 is used, for example, at a gate-source voltage Vgs of 10 mV to 30 mV and a drain-source voltage Vds of 2 V.
In such a case, in the J-FET having the source region 25, the drain region 26, and the gate region 27 arranged in the stripe pattern, the source region 25, the drain region 26, and the gate region 27 are often disposed so that a distance between the gate region 27 and the drain region 26 (hereinafter, G-D distance L21) can be larger than a distance between the gate region 27 and the source region 25 (hereinafter, G-S distance L22), as shown in FIG. 5B.
A large bias voltage is applied between the gate region 27 and the drain region 26 compared to that applied between the gate region 27 and the source region 25. Accordingly, a width d1 of a depletion layer expanding from the gate region 27 toward the drain region 26 results in being larger than a width d2 of a depletion layer expanding from the gate region 27 toward the source region 25.
In short, a pattern in which the G-D distance L21 is larger than the G-S distance L22 is used so that expansion of the depletion layer d may not be interfered.
One of the essential parameters of the J-FET is forward transfer admittance gm. The forward transfer admittance gm is proportional to a gate width. In other words, to increase the forward transfer admittance gm, a large gate width is needed, and, consequently, the length of the gate region 27 disposed in the channel region 24 needs to be increased.
FIG. 6 illustrates a J-FET 200′ in which gate regions 27 are disposed in a grid pattern. Sets of parallel gate regions 27 intersect to form the grid pattern. Source regions 25 and drain regions 26 spaced from each other and each provided as an island are disposed respectively in portions of channel region 24, the portions being surrounded by the gate regions 27. In this grid pattern, the source regions 25 and the drain regions 26 are alternately disposed in matrix in order to dispose source electrodes 29 and drain electrodes 30 as shown by the dashed lines.
Assuming that the area of the single channel region 24 (hereinafter, referred to as box B) isolated as an island by an isolation region 23 in this case is equal to that of the single channel region 24 in the case where the gate region 27 is disposed in the stripe pattern as shown in FIGS. 4 and 5. Then, the gate width can be approximately doubled in this case, compared with the case shown in FIGS. 4 and 5.
However, in this case, at least the gate regions 27 extending in the same direction need to be disposed at an equal interval “a”. Accordingly, since the source regions 25 and the drain regions 26 are alternately disposed as described above, a G-D distance L21′ and a G-S distance L22′ cannot be different, unlike the case employing the stripe pattern. Thus, since the withstand voltage depends on the G-D distance L21′, it is necessary to enlarge the area of the box B in order to ensure a predetermined withstand voltage.
Since the J-FET 200′ of the above-described configuration has a back gate structure (see FIG. 5A), the area of the box B is a junction area of a p type back gate region (p type semiconductor layer 22) and the n type channel region 24. Accordingly, an increase in the area of the box B leads to an increase in gate junction capacitance, and an increase in input capacitance Ciss consequently causes deterioration in switching characteristics.